Multioperand Redundant Adders on FPGAs-Reference-Cited by-同舟云学术

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Multioperand Redundant Adders on FPGAs

Published:2013-10 Issue:10 Volume:62 Page:2013-2025
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Hormigo Javier,Villalba Julio,Zapata Emilio L.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx5/12/6585338/06235949.pdf?arnumber=6235949

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Study of Area-delay and Energy Efficient Multi-operand Binary Tree Adder;Lecture Notes in Electrical Engineering;2022-09-04

2. Efficient Fused MAC Unit Using Multi-Operand Parallel Prefix Adder;Radioelectronics and Communications Systems;2022-04

3. A faster approach to add Multi operands using unified pipelining technique;Materials Today: Proceedings;2021-04

4. Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm;Lecture Notes in Electrical Engineering;2020-06-24

5. Methods of On-Line Computation Acceleration in Systems with Direct Connection between Units;2020 IEEE 11th International Conference on Dependable Systems, Services and Technologies (DESSERT);2020-05

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