Efficient Fused MAC Unit Using Multi-Operand Parallel Prefix Adder
Author:
Publisher
Allerton Press
Subject
Electrical and Electronic Engineering
Link
https://link.springer.com/content/pdf/10.3103/S0735272722040057.pdf
Reference20 articles.
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3. K. R. Gavali, N. Choudhary, S. Mishra, S. Dubey, "A parallel pipelined adder suitable for FPGA implementation," in 2018 International Conference on Smart City and Emerging Technology (ICSCET) (IEEE, 2018). DOI: https://doi.org/10.1109/ICSCET.2018.8537358.
4. S. Kannappan, S. Aruna Mastani, "A novel multi-operand adder design using multiplexers," in 2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC) (IEEE, 2017). DOI: https://doi.org/10.1109/ICCIC.2017.8524157.
5. R. D. Kenney, M. J. Schulte, "High-speed multioperand decimal adders," IEEE Trans. Comput., v.54, n.8, p.953 (2005). DOI: https://doi.org/10.1109/TC.2005.129.
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