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Chip–Package Interaction and Reliability Improvement by Structure Optimization for Ultralow-$k$ Interconnects in Flip-Chip Packages

  • Published:2012-06 Issue:2 Volume:12 Page:462-469
  • ISSN:1530-4388
  • Container-title:IEEE Transactions on Device and Materials Reliability
  • language:
  • Short-container-title:IEEE Trans. Device Mater. Relib.

Author:

Zhang Xuefeng,Wang Yiwei,Im Jang-Hi,Ho Paul S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials

Cited by 26 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Study on ELK Dielectric Reliability During the Solder Reflow Process Based on Finite Element Simulations;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17

2. An Investigation on the Most Likely Failure Locations in the BEoL Stack of a 20 nm Chip Due to Chip Package Interaction with the Use of Novel Semi-Elliptical Cracks;Micromachines;2023-10-19

3. The characterization of low-k thin films and their fracture analysis in a WLCSP device;Microelectronics Reliability;2023-09

4. Mechanical Robustness of Patterned Structures and Failure Mechanisms;More-than-Moore Devices and Integration for Semiconductors;2023

5. Development and Verification of Effective Layer Function for Simulating Flip-Chip Packages;2022 IEEE 14th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment, and Management (HNICEM);2022-12-01
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