An Investigation on the Most Likely Failure Locations in the BEoL Stack of a 20 nm Chip Due to Chip Package Interaction with the Use of Novel Semi-Elliptical Cracks

Abstract

The era of 20 nm integrated circuits has arrived. There exist abundant heterogeneous micro/nano structures, with thicknesses ranging from hundreds of nanometers to sub-microns in the IC back end of the line stack, which put stringent demands on the reliability of the device. In this paper, the reliability issues of a 20 nm chip due to chip–package interaction during the reflow process is studied. A representative volume element of the detailed complex BEoL structure has been analyzed to obtain mechanical properties of the BEoL stack by adopting a sub-model analysis. For the first time, semi-elliptical cracks were used in conjunction with J-integral techniques to analyze the failure caused by Chip-to-Package Interaction for a 20 nm chip. The Energy Release Rate(ERR)for cracks at various interfaces and locations in the BEoL stack were calculated to predict the most likely mode and location of failure. We found that the ERR of interfacial cracks at the bottom surface of the interconnects are, on average, more than double those at the sidewalls, which are in turn more than double the number of cracks in the low-k inter-layer dielectric. A total of 500 cycles of thermal shock were conducted, which verified the predictions of the finite element simulations.