GeSn Vertical Gate-all-around Nanowire n-type MOSFETs
Author:
Affiliation:
1. Peter-Grünberg-Institut (PGI-9), Forschungszentrum Jülich,Jülich,Germany
2. CEA-LETI, MINATEC Campus and University of Grenoble Alps,Grenoble,France
Funder
BMBF
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9947060/9947094/09947133.pdf?arnumber=9947133
Reference22 articles.
1. Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
2. Considerations for Ultimate CMOS Scaling
3. (Invited) Vertical Nanowire FET Integration and Device Aspects
4. Lateral versus vertical gate-all-around FETs for beyond 7nm technologies
5. A Bandpass Filter Incorporated Into the Inductor Current Feedback Path for Improving Dynamic Performance of the Front-End DC–DC Converter in Two-Stage Inverter
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1. Research progress of out-of-plane GeSn nanowires;Nanotechnology;2024-03-26
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