A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters
Author:
Affiliation:
1. Politecnico di Milano,Milan,Italy
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9841660/9841947/09842195.pdf?arnumber=9842195
Reference18 articles.
1. Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs
2. Rapid calibration of bits weights error for high‐resolution successive approximation register ADC
3. Analysis and Design of Regenerative Comparators for Low Offset and Noise
4. A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s
5. A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters
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1. A 12-bit 50MS/s SAR ADC with non-binary split capacitive DAC in 40nm CMOS;IEICE Electronics Express;2024-08-25
2. A 150 MS/s, 10 bit SAR ADC Featuring a Modified Quasi-Monotonic Switching Scheme;2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2024-06-09
3. A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk;IEEE Journal of Solid-State Circuits;2024
4. A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC With Charge Linearization;IEEE Transactions on Circuits and Systems II: Express Briefs;2023
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