Rapid calibration of bits weights error for high‐resolution successive approximation register ADC-Reference-Cited by-同舟云学术

Rapid calibration of bits weights error for high‐resolution successive approximation register ADC

Published:2019-04-15 Issue:3 Volume:13 Page:368-373
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Liu Lu¹²,Xu Daiguo²,Xu Shiliu¹

Affiliation:

1. University of Electronic Science and Technology of China, the school of Microelectronics and Solid‐state ElectronicsChengdu611731People's Republic of China

2. The Key Laboratory of Analogy Integrated CircuitChongqing400060People's Republic of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2018.5220

Reference20 articles.

1. Li H. Maddox M. Michael C. et al.: ‘A signal‐independent background‐calibrating 20 b 1 MS/s SAR ADC with 0.3 ppm INL’.Int. Solid‐State Circuits Conf. February2018 pp.242–244

2. A 16 bit 16 MS/s SAR ADC with on‐chip calibration in 55 nm CMOS;Shen J.;IEEE J. Solid‐State Circuits Biol.,2017

3. An 18 b 12.5 MS/s ADC With 93 dB SNR

4. LMS based adaptive bit weights error extraction algorithm used in high resolution A/D converters

5. All‐digital background calibration of a successive approximation ADC using the ‘split ADC’ architecture;McNeill J.;IEEE TCAS‐I,2011

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Simulation and Comparative Analysis of Dynamic Comparators at 1MHz for Biomedical Applications;2022 3rd International Conference on Issues and Challenges in Intelligent Computing Techniques (ICICT);2022-11-11

2. A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters;2022 20th IEEE Interregional NEWCAS Conference (NEWCAS);2022-06-19

3. A Noise Reduction 12-bit 125-MSPS SAR ADC with Modified Asynchronous Logic Regulation Technique;Journal of Circuits, Systems and Computers;2020-08-08

4. Median Selection for Calibrating the Capacitor Mismatch to Improve the Linearity of Analog-to-Digital Converter;Circuits, Systems, and Signal Processing;2020-05-10