Row-buffer decoupling: A case for low-latency DRAM microarchitecture
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IEEE
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http://xplorestaging.ieee.org/ielx7/6847316/6853187/06853230.pdf?arnumber=6853230
Cited by 26 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29
2. FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration;ACM Transactions on Architecture and Code Optimization;2024-05-21
3. Improving Performance of Network-on-Memory Architectures via (De-)/Compression-in-DRAM;Proceedings of the 2023 ACM International Workshop on System-Level Interconnect Pathfinding;2023-11-02
4. CoolDRAM: An Energy-Efficient and Robust DRAM;2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED);2023-08-07
5. CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09
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