CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays-Reference-Cited by-同舟云学术

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CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays

Published:2023-07-09 Issue: Volume: Page:
ISSN:
Container-title:2023 60th ACM/IEEE Design Automation Conference (DAC)
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Author:

Wang Chengning¹,Feng Dan¹,Tong Wei¹,Liu Jingning¹

Affiliation:

1. Huazhong University of Science and Technology,Wuhan National Laboratory for Optoelectronics, Key Laboratory of Information Storage System, Engineering Research Center of Data Storage Systems and Technology, Ministry of Education of China School of Computer Science and Technology,Wuhan,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10247654/10247655/10247700.pdf?arnumber=10247700

Reference26 articles.

1. JEDEC Standard: DDR4 SDRAM;JESD79-4D,2021

2. A case for exploiting subarray-level parallelism (SALP) in DRAM

3. Improving write performance on cross-point RRAM arrays by leveraging multidimensional non-uniformity of cell effective voltage;wang;IEEE TC,2020

4. Row-buffer decoupling: A case for low-latency DRAM microarchitecture

5. Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects

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