Improving Performance of Network-on-Memory Architectures via (De-)/Compression-in-DRAM-Reference-Cited by-同舟云学术

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Improving Performance of Network-on-Memory Architectures via (De-)/Compression-in-DRAM

Published:2023-11-02 Issue: Volume: Page:1-10
ISSN:
Container-title:Proceedings of the 2023 ACM International Workshop on System-Level Interconnect Pathfinding
language:
Short-container-title:

Author:

Mohammadhassani Arghavan¹^ORCID,Das Anup¹^ORCID

Affiliation:

1. Drexel University, Philadelphia, USA

Funder

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3632409.3640477

Reference24 articles.

1. [n.d.].

2. Alaa R. Alameldeen and David A. Wood. 2007. Interactions Between Compression and Prefetching in Chip Multiprocessors. In HPCA.

3. Russell Croston Aubusson. 1979. Wafer-scale integration of semiconductor memory. Ph. D. Dissertation. Middlesex Polytechnic.

4. Shekhar Borkar. 2007. Thousand Core Chips: A Technology Perspective. In DAC.

5. Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, et al. 2015. Noxim: An open, extensible and cycle-accurate network on chip simulator. In ASAP.

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