Reducing power dissipation in CMOS circuits by signal probability based transistor reordering-Reference-Cited by-同舟云学术

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Reducing power dissipation in CMOS circuits by signal probability based transistor reordering

Published:1996-03 Issue:3 Volume:15 Page:361-368
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Hossain R.,Zheng M.,Albicki A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx1/43/10539/00489107.pdf?arnumber=489107

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Transistor Reordering for Electrical Improvement in CMOS Complex Gates;2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2022-08-22

2. Transistor and pin reordering for leakage reduction in CMOS circuits;Microelectronics Journal;2016-07

3. Comparative analysis of yield optimized pulsed flip-flops;Microelectronics Reliability;2012-08

4. Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis;Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation;2011

5. A new approach to power estimation and reduction in CMOS digital circuits;Integration;2008-02

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