Comparative analysis of yield optimized pulsed flip-flops-Reference-Cited by-同舟云学术

Comparative analysis of yield optimized pulsed flip-flops

Published:2012-08 Issue:8 Volume:52 Page:1679-1689
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Lanuzza Marco,Rose Raffaele De,Frustaci Fabio,Perri Stefania,Corsonello Pasquale

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference24 articles.

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3. Sylvester D, Agarwal K, Shah S. Invited paper: Variability in nanometer CMOS: impact, analysis, and minimization. Integration, the VLSI Journal 2008; 41(3): 319–339.

4. Comparative analysis of master–slave latches and flip-flops for high-performance and low-power systems;Stojanovic;IEEE J Solid-State Circuits,1999

5. B. Rebaud, M.Belleville, C. Bernard, M. Robert, P. Maurine, N. Azemard. A comparative study of variability impact on static flip-flop timing characteristics. In: Proc. IEEE international conference on integrated circuit design and technology (ICICDT), Austin, TX, 2–4 June 2008. pp. 167–170.

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