Self-Heating and Interface Traps Assisted Early Aging Revelation and Reliability Analysis of Negative Capacitance FinFET
Author:
Affiliation:
1. PDPM-IIITDM Jabalpur,India
2. IIT Roorkee,India
3. VIT Chennai,India
4. Korea Military Academy,Seoul,Korea
5. IIT Bhubaneswar,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10102927/10102928/10103127.pdf?arnumber=10103127
Reference8 articles.
1. Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs
2. Impact of Self-Heating on Negative-Capacitance FinFET: Device-Circuit Interaction
3. Reliability of TCAD study for HfO2-doped Negative capacitance FinFET with different Material-Specific dopants
4. High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization
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