A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS-Reference-Cited by-同舟云学术

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A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS

Published:2020-03 Issue:3 Volume:55 Page:580-591
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Pfaff Dirk^ORCID,Abbott Robert^ORCID,Wang Xin-Jie,Moazzeni Shahaboddin^ORCID,Mason Ralph^ORCID,smith Raleigh R.^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9011683/08894653.pdf?arnumber=8894653

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2. 3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

3. 7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

4. A 14 GHz Integer-N Sub-Sampling PLL With RMS-Jitter of 85.4 fs Occupying an Ultra Low Area of 0.0918 mm²;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02

5. An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

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