7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS-Reference-Cited by-同舟云学术

7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS

Published:2024-02-18 Issue: Volume: Page:128-130
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Container-title:2024 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Pfaff Dirk¹,Nummer Muhammad¹,Hai Noman²,Xia Peter²,Yang Kai Ge²,Mohsenpour Mohammad-Mahdi¹,LaCroix Marc-Andre¹,Zamanlooy Babak³,Eeckelaert Tom¹,Petrov Dmitry¹,Haroun Mostafa¹,Dick Carson²,Zaman Alif¹,Mei Haitao¹,Moazzeni Shahab¹,Shakir Tahseen¹,Carvalho Carlos¹,Huang Howard¹,Kumari Pratibha¹,Mason Ralph¹,Brishty Fahmida²,Jaffri Ifrah²

Affiliation:

1. Synopsys,Ottawa,Canada

2. Synopsys,Mississauga,Canada

3. Synopsys,Markham,Canada

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454537.pdf?arnumber=10454537

Reference6 articles.

1. A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS

2. 8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2

3. A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET

4. 8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS

5. An output-bandwidth-optimized 200 Gb/s PAM-4 100 Gb/s NRZ transmitter with 5-tap FFE in 28 nm CMOS;Choi

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1. A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers;IEEE Transactions on Circuits and Systems I: Regular Papers;2024