3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction-Reference-Cited by-同舟云学术

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3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction

Published:2024-09 Issue:9 Volume:71 Page:4091-4095
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Park Gijin¹^ORCID,Yeom Sunoh²,Jang In-Woo³^ORCID,Lee Dongjun²^ORCID,Han Jaeduk²^ORCID,Choo Min-Seong³^ORCID

Affiliation:

1. Electrical Engineering Department, Analog and Mixed Signal Center, Texas A&M University at College Station, College Station, TX, USA

2. Department of Electronic Engineering, Hanyang University, Seoul, South Korea

3. School of Electrical Engineering, Hanyang University, Ansan, South Korea

Funder

Samsung

Samsung Research Funding and Incubation Center

National Research Foundation of Korea

Korea Government

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8920/10666887/10507171.pdf?arnumber=10507171

Reference16 articles.

1. A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS

2. 11.5 A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET

3. Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops

4. An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection

5. A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques

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