A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/7368951/7210238.pdf?arnumber=7210238
Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell;IEEE Journal of Solid-State Circuits;2024-01
2. Integration;Handbook of Integrated Circuit Industry;2023-11-28
3. CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09
4. eDRAM-OESP: A novel performance efficient in-embedded-DRAM-compute design for on-edge signal processing application;2023 24th International Symposium on Quality Electronic Design (ISQED);2023-04-05
5. eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters;IEEE Journal of Solid-State Circuits;2023
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