1. K. Mistry, C. Allen, C. Auth, et al., A 45 nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging, in IEDM 2007, Washington, DC, December 10–12, 2007, (IEEE, Washington, DC, 2007)
2. C.H. Jan, M. Agostinelli, H. Deshpande, et al., RF CMOS Technology scalking in high-k/metal gate era for RF SoC (System-on-Chip) applications, in IEDM 2010, San Francisco, December 6–8, 2010, (IEEE, San Francisco, 2010)
3. K.Y. Lim, H. Lee, C. Ryu, et al., Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices, in IEDM 2010, San Francisco, December 6–8, 2010, (IEEE, San Francisco, 2010)
4. C. Auth, A. Cappellani, J.S. Chun, et al., 45 nm high-k + metal gate strain-enhanced transistors, in VLSI 2008, Honolulu, June 17–19, 2008, (IEEE, Honolulu, 2008)
5. S. Natarajan, M. Agostinelli, S. Akbar, et al., A 14 nm logic technology featuring 2nd –generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm2 SRAM cell size, in IEDM 2014, San Francisco, December 15–17, 2014, (IEEE, San Francisco, 2014)