A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise-Reference-Cited by-同舟云学术

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A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise

Published:2018-07 Issue:7 Volume:53 Page:1902-1912
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Bindra Harijot Singh^ORCID,Lokin Christiaan E.^ORCID,Schinkel Daniel^ORCID,Annema Anne-Johan^ORCID,Nauta Bram^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8396884/08345180.pdf?arnumber=8345180

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