Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM-Reference-Cited by-同舟云学术

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Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM

Published:2012-04 Issue:4 Volume:47 Page:969-980
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Chen Yen-Huei,Chou Shao-Yu,Li Quincy,Chan Wei-Min,Sun Dar,Liao Hung-Jen,Wang Ping,Chang Meng-Fan,Yamauchi Hiroyuki

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/6173080/06151870.pdf?arnumber=6151870

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Threshold Voltage Deviation Monitoring Scheme of Bit Transistors in 6T SRAM for Manufacturing Defects Detection;IEEE Transactions on Semiconductor Manufacturing;2024-05

2. Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design;Microelectronics Journal;2023-02

3. Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-07

4. A Novel Design of 28 nm Latch Type Sense Amplifier for Differential Voltage Enhancement;IETE Journal of Research;2020-12-27

5. MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing;IEEE Transactions on Circuits and Systems II: Express Briefs;2020-12

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