A Threshold Voltage Deviation Monitoring Scheme of Bit Transistors in 6T SRAM for Manufacturing Defects Detection
Author:
Affiliation:
1. Institute of VLSI Design, Zhejiang University, Hangzhou, China
2. Technology Department, Pantum Electronics Company Ltd., Zhuhai, China
Funder
China National Key Research and Development Program
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/66/10521908/10496911.pdf?arnumber=10496911
Reference21 articles.
1. 11 2008 676 676 4666783 10.1109/TSM.2008.2008790 http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=4666783
2. Accurate Estimation of SRAM Dynamic Stability
3. Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM
4. Large-Scale SRAM Variability Characterization in 45 nm CMOS
5. In Situ SRAM Static Stability Estimation in 65-nm CMOS
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