250 Mbps–5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 $\mu$m CMOS-Reference-Cited by-同舟云学术

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250 Mbps–5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 $\mu$m CMOS

Published:2011-11 Issue:11 Volume:46 Page:2560-2570
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Lee Sang-Yoon,Lee Hyung-Rok,Kwak Young-Ho,Choi Woo-Seok,Yoo Byoung-Joo,Shim Daeyun,Kim Chulwoo,Jeong Deog-Kyoon

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/6056707/06007146.pdf?arnumber=6007146

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2022-02

2. A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS;IEEE Journal of Solid-State Circuits;2021-05

3. A Low-power 3.52 Gbps SerDes with a MDLL Frequency Multiplier for High-speed On-chip Networks;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2018-12-31

4. A High-speed SerDes Transceiver for Wireless Proximity Communication;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2018-02-28

5. Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process;International Journal of Circuit Theory and Applications;2016-09-16

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