Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process-Reference-Cited by-同舟云学术

Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process

Published:2016-09-16 Issue:6 Volume:45 Page:851-858
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int. J. Circ. Theor. Appl.

Author:

Wang Yuan¹^ORCID,Liu Yuequan¹,Jia Song¹,Zhang Xing¹

Affiliation:

1. Key Laboratory of Microelectronic Devices and Circuits (MoE); Institute of Microelectronics, Peking University; 100871 Beijing China

Funder

National High Technology Research and Development Program of China

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference15 articles.

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2. A 20 Gb/s clock and data recovery with a Ping-Pong delay line for unlimited phase shifting in 65 nm CMOS process;Kwak;IEEE Transactions on Circuits and System-I: Regular Papers,2013

3. Jitter and phase noise in ring oscillators;Hajimiri;IEEE Journal of Solid-State Circuits,1999

4. Cheng LJ Lin QY The performances comparison between DLL and PLL based RF CMOS oscillators Proceeding of International Conference on ASIC 2001 827 830

5. An all-digital phase-locked loop for high-speed clock generation;Chung;IEEE Journal of Solid-State Circuits,2003

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