A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS-Reference-Cited by-同舟云学术

A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS

Published:2022-02 Issue:2 Volume:57 Page:546-561
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Zhao Xiaoteng^ORCID,Chen Yong^ORCID,Mak Pui-In^ORCID,Martins Rui P.^ORCID

Funder

Guangzhou Science and Technology Innovation and Development of Special Funds

Macau Science and Technology Development Fund (FDCT) through the SKL Fund

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9694622/09552437.pdf?arnumber=9552437

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