A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS-Reference-Cited by-同舟云学术

A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS

Published:2014-12 Issue:12 Volume:49 Page:3091-3103
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kimura Hiroshi,Aziz Pervez M.,Jing Tai,Sinha Ashutosh,Kotagiri Shiva Prasad,Narayan Ram,Gao Hairong,Jing Ping,Hom Gary,Liang Anshi,Zhang Eric,Kadkol Aniket,Kothari Ruchi,Chan Gordon,Sun Yehui,Ge Benjamin,Zeng Jason,Ling Kathy,Wang Michael C.,Malipatil Amaresh,Li Lijun,Abel Christopher,Zhong Freeman

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6963535/06894632.pdf?arnumber=6894632

Cited by 43 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation;IEEE Journal of Solid-State Circuits;2024-08

2. Minimum Power Point Design of Inverter Based Continuous Time Linear Equalizer (CTLE);2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. A 32Gb/s Equalizer with Adaptive T-Coil Input Matching and Fullrate DFE in 28nm CMOS;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22

4. Asynchronous Sampling-Based Hybrid Equalizer;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-07

5. A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO;IEICE Electronics Express;2022-12-25