A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO-Reference-Cited by-同舟云学术

A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO

Published:2022-12-25 Issue:24 Volume:19 Page:20220432-20220432
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Pan Chengxian¹,Shi Chunqi¹,Zhao Guoliang²,Liu Boxiao¹,Huang Leilei¹,Zhang Runxi¹

Affiliation:

1. Institute of Microelectronic Circuits and Systems, East China Normal University

2. The Research Institute 214 of China North Industries Group Corporation

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/19/24/19_19.20220432/_pdf

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