Design and Analysis of High-Throughput Two-Cycle Multiply-Accumulate (MAC) Architectures for Fixed-Point Arithmetic
Author:
Affiliation:
1. Indian Institute of Engineering Science and Technology (IIEST) Shibpur,Howrah,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10059459/10059604/10059958.pdf?arnumber=10059958
Reference20 articles.
1. Performance Analysis of Vedic Multiplier with Different Square Root BK Adders
2. Conventional versus Vedic Mathematical Method for Hardware Implementation of a Multiplier
3. Design of High-Speed 32-Bit Vedic Multiplier Using Verilog HDL
4. Fast Energy Efficient Radix-16 Sequential Multiplier
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