A 33-ppm/°C 240-nW 40-nm CMOS Wakeup Timer Based on a Bang-Bang Digital-Intensive Frequency-Locked-Loop for IoT Applications
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/9127215/09036068.pdf?arnumber=9036068
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Energy Efficient and Temperature Stable Digital FLL-Based Wakeup Timer With Time-Domain Temperature Compensation;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07
2. A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02
3. CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12
4. A 0.4-V 0.0294-mm2 Resistor-Based Temperature Sensor Achieving ±0.24 °C p2p Inaccuracy From40 °C to 125 °C and 385 fJ · K2 Resolution FoM in 65-nm CMOS;IEEE Journal of Solid-State Circuits;2023-09
5. Design and Analysis of a Resistive Frequency-Locked Oscillator With Long-Term Stability Using Double Chopper Stabilization;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-02
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