Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond
Author:
Affiliation:
1. Department of Electronic Engineering, ETSI de Telecomunicación, Universidad Politécnica de Madrid (UPM), Madrid, Spain
Funder
MCIN/AEI/10
“ERDF-A way of making Europe”
“ESF-Investing in your future”
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/10268488/10202997.pdf?arnumber=10202997
Reference32 articles.
1. Multiplierless Unity-Gain SDF FFTs
2. Hardware architectures for the fast Fourier transform
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4. Radix $r^{k} $ FFTs: Matricial Representation and SDC/SDF Pipeline Implementation
5. Reconfigurable Constant Multiplication for FPGAs
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