Optimized 4-Parallel 1024-Point MSC FFT
Author:
Affiliation:
1. Department of Electricity and Energy, Osmaneli Vocational School, Bilecik Şeyh Edebali University, Bilecik, Turkey
2. Department of Electronic Engineering, ETSI de Telecomunicación, Universidad Politécnica de Madrid, Madrid, Spain
Funder
Comunidad de Madrid through the Call “Ayudas de Estímulo a la Investigación de Jóvenes Doctores de la Universidad Politécnica de Madrid”
“European Social Fund (ESF) Investing in Your Future”
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx8/6287639/10380310/10557595.pdf?arnumber=10557595
Reference45 articles.
1. Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond
2. A low latency and area efficient FFT processor for massive MIMO systems
3. Digital Spectro-Correlator System for the Atacama Compact Array of the Atacama Large Millimeter/Submillimeter Array
4. A 1 Million-Point FFT on a Single FPGA
5. Doppler Frequency Estimation in GNSS Receivers Based on Double FFT
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