Evaluation of I-Cache Locking Technique for Real-Time Embedded Systems
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4430361/4430362/04430406.pdf?arnumber=4430406
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design Guidelines for Low Power Embedded Systems using Low Power Electronics;WSEAS TRANSACTIONS ON ELECTRONICS;2023-11-20
2. Aligning single path loops to reduce the number of capacity cache misses;ACM SIGBED Review;2015-03-27
3. A real-time capable coherent data cache for multicores;Concurrency and Computation: Practice and Experience;2013-10-17
4. Instruction cache locking for multi-task real-time embedded systems;Real-Time Systems;2011-10-21
5. Improving cache locking performance of modern embedded systems via the addition of a miss table at the L2 cache level;Journal of Systems Architecture;2010-04
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