A real-time capable coherent data cache for multicores

Author:

Pyka Arthur1,Rohde Mathias1,Uhrig Sascha1

Affiliation:

1. Technical University of Dortmund; Germany

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Reference26 articles.

1. A survey of cache coherence schemes for multiprocessors;Stenstrom;Computer,1990

2. Hardware approaches to cache coherence in shared-memory multiprocessors, part 1;Tomasevic;IEEE Micro,1994

3. OpenSPARC T2 implementation supplement, hyperprivileged edition 2007 http://www.opensparc.net/docs/OST2-UASuppl-current-draft-HP-EXT.pdf

4. An introduction to the intel quickpath interconnect 2007 http://www.intel.com/technology/quickpath/introduction.pdf

5. Cache hierarchy and memory subsystem of the amd opteron processor;Conway;IEEE Micro,2010

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4. Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore;ACM Transactions on Embedded Computing Systems;2016-07-21

5. MESI-Based Cache Coherence for Hard Real-Time Multicore Systems;Lecture Notes in Computer Science;2015

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