Consideration of UFET Architecture for the 5 nm Node and Beyond Logic Transistor-Reference-Cited by-同舟云学术

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Consideration of UFET Architecture for the 5 nm Node and Beyond Logic Transistor

Published:2018 Issue: Volume:6 Page:1129-1135
ISSN:2168-6734
Container-title:IEEE Journal of the Electron Devices Society
language:
Short-container-title:IEEE J. Electron Devices Soc.

Author:

Das Uttam Kumar^ORCID,Eneman Geert,Velampati Ravi Shankar R.,Chauhan Yogesh Singh^ORCID,Jinesh K. B.,Bhattacharyya Tarun K.^ORCID

Funder

Department of Space, Govt. of India

Department of Science and Technology, Govt. of India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials,Biotechnology

Link

http://xplorestaging.ieee.org/ielx7/6245494/8232486/08466575.pdf?arnumber=8466575

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Sensitivity enhancement using triple metal gate work function engineering of junctionless cylindrical gate all around SiNW MOSFET based biosensor for neutral biomolecule species detection for upcoming sub 14 nm technology node;Materials Science and Engineering: B;2024-08

2. DC and Analog/RF Performance Evaluation Using Dual Metal Gate Work Function Engineering of Junctionless Cylindrical Gate All Around Si Nanowire MOSFET Using NEGF Approach for Upcoming Sub 5 nm Technology Node;International Journal of Precision Engineering and Manufacturing;2024-05-31

3. Impact of ambient temperature on CombFET for sub-5-nm technology nodes: An RF performance perspective;Microsystem Technologies;2024-05-18

4. Triple-metal gate work function engineering to improve the performance of junctionless cylindrical gate-all-around Si nanowire MOSFETs for the upcoming sub-3-nm technology node;Journal of Computational Electronics;2024-04

5. Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective;IEEE Access;2024

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