Optimisation of the carrier lifetime profile in 1.2kV planar and trench SiC MOSFETs
Author:
Affiliation:
1. University of Cambridge,Department of Engineering,Cambridge,UK,CB3 0FA
2. Hitachi Energy, Semiconductors,Lenzburg,Switzerland,CH-5600
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9813543/9813532/09813631.pdf?arnumber=9813631
Reference10 articles.
1. Lifetime-killing defects in 4H-SiC epilayers and lifetime control by low-energy electron irradiation
2. 6.5 kV Schottky-Barrier-Diode-Embedded SiC-MOSFET for Compact Full-Unipolar Module;kawahara;29th ISPSD,2019
3. Numerical analysis of local lifetime control for high-speed low-loss P-i-N diode design
4. Wide-ranging control of carrier lifetimes in n-type 4H-SiC epilayer by intentional vanadium doping
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