Design and implementation of floating point multiplier based on Vedic Multiplication Technique-Reference-Cited by-同舟云学术

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Design and implementation of floating point multiplier based on Vedic Multiplication Technique

Published:2012-10 Issue: Volume: Page:
ISSN:
Container-title:2012 International Conference on Communication, Information & Computing Technology (ICCICT)
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Author:

Kanhe Aniruddha,Das Shishir Kumar,Singh Ankit Kumar

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6387505/6398085/06398204.pdf?arnumber=6398204

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 64 BIT MAC Unit Design based on FPGA Using Vedic Multiplier;2023 Global Conference on Information Technologies and Communications (GCITC);2023-12-01

2. High-Speed Vedic Multiplier Implementation Using Memristive and Speculative Adders;2022 International Conference on Computing, Communication and Power Technology (IC3P);2022-01

3. FPGA Implementation of Parallel Adder Using Reversible Logic Gates;Micro-Electronics and Telecommunication Engineering;2021

4. Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm;Lecture Notes in Electrical Engineering;2020-06-24

5. Low-Power and Area-Efficient Design of Higher-Order Floating-Point Multipliers Using Vedic Mathematics;Lecture Notes in Electrical Engineering;2019-09-25

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