FPGA Implementation of Parallel Adder Using Reversible Logic Gates-Reference-Cited by-同舟云学术

FPGA Implementation of Parallel Adder Using Reversible Logic Gates

Published:2021 Issue: Volume: Page:429-435
ISSN:2367-3370
Container-title:Micro-Electronics and Telecommunication Engineering
language:
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Author:

Yuvaraj S. A.,Gunasekaran K.,Muthukumaran D.,Umapathy K.

Publisher

Springer Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-33-4687-1_40

Reference17 articles.

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3. Anitha, R., Neha, D., Prashant, A., Sarat, K.S., Prabhakar Karthikeyan, S., Jacob Reglend, I.: A 32 bit mac unit design using vedic multiplier and reversible logic gate. In: 2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015], pp. 1–6. IEEE (2015)

4. Ramalatha, M., Deena Dayalan, K., Dharani, P., Deborah Priya, S.: High speed energy efficient ALU design using Vedic multiplication techniques. In: 2009 International Conference on Advances in Computational Tools for Engineering Applications, pp. 600–603. IEEE (2009)

5. Kayalvizhi, N.: Implementation of power efficient vedic multiplier. Int. J. Comput. Appl. 43(16) (2012)

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