A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate-Reference-Cited by-同舟云学术

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A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate

Published:2015-03 Issue: Volume: Page:
ISSN:
Container-title:2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]
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Author:

Anitha R.,Deshmukh Neha,Agarwal Prashant,Sahoo Sarat Kumar,Karthikeyan S. Prabhakar,Reglend I. Jacob

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7147630/7159156/07159505.pdf?arnumber=7159505

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-End Approximate Multiplier Using Brent Kung Razor FlipFlop;2024 5th International Conference for Emerging Technology (INCET);2024-05-24

2. FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing;Journal of Circuits, Systems and Computers;2024-04-10

3. A nano-scale design of a multiply-accumulate unit for digital signal processing based on quantum computing;Optical and Quantum Electronics;2023-11-23

4. Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module;International Journal of Electrical and Electronics Research;2022-12-30

5. Efficient Implementation of Cryptographic Arithmetic Primitives Using Reversible Logic and Vedic Mathematics;Journal of The Institution of Engineers (India): Series B;2021-01-08

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