A fully planarized 0.25 μm CMOS technology for 256 Mbit DRAM and beyond-Reference-Cited by-同舟云学术

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A fully planarized 0.25 μm CMOS technology for 256 Mbit DRAM and beyond

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Container-title:1995 Symposium on VLSI Technology. Digest of Technical Papers
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Author:

Bronner G.,Aochi H.,Gall M.,Gambino J.,Gernhardt S.,Hammerl E.,Ho H.,Iba J.,Ishiuchi H.,Jaso M.,Kleinhenz R.,Mii T.,Narita M.,Nesbit L.,Neumueller W.,Nitayama A.,Ohiwa T.,Parke S.,Ryan J.,Sato T.,Takato H.,Yoshikawa S.

Publisher

Japan Soc. Appl. Phys

Link

http://xplorestaging.ieee.org/ielx3/4018/11536/00520837.pdf?arnumber=520837

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A TiO$$_2$$ S/D n-channel FD-SOI MOSFET-based zero capacitor random access memory device;Journal of Computational Electronics;2020-10-06

2. Effect of substrate temperature on sidewall erosion in high-aspect-ratio Si hole etching employing HBr/SF6/O2 plasma;Japanese Journal of Applied Physics;2018-08-06

3. High rate deep Si etching for through-silicon via applications;Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films;2011-03

4. High Performance Embedded Dynamic Random Access Memory in Nano-Scale Technologies;CMOS Processors and Memories;2010

5. High yielding self-aligned contact process for a 0.150-μm DRAM technology;IEEE Transactions on Semiconductor Manufacturing;2002-05

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