1. T. Kirihata, G. Mueller, B. Ji, G. Frankowsky, J. Ross, H. Terletzki, D. Netis, O. Weinfurtner, D. Hanson, G. Daniel, L. Hsu, D. Storaska, A. Reith, M. Hug, K. Guay, M. Selz, P. Poechmueller, H. Hoenigschmid, M. Wordeman, A 390 mm2, 16-Bank, 1 Gb DDR SDRAM with Hybrid Bitline Architecture. JSCC 34, 1580–1588 (1999).
2. ISSCC Dig. Tech. Papers;T Murotani,1997
3. H.S. Jeong, W.S. Yang, T.S. Hwang, C.H. Cho, S. Park, S.J. Ahn, Y.S. Chun, S.H. Shin, S.H. Song, J.Y. Lee, S.M. Jang, C.H. Lee, J.H. Jeong, M.H. Cho, J.K. Lee, H.S. Kinam Kim, Highly manufactuable 4Gb DRAM using 0.11μm DRAM technology, IEDM Dig. Tech. Papers, Dec 2000, pp. 353–356.
4. T. Kirihata, Embedded dynamic random access memory, VLSI technology, systems, and applications, Dig. Tech. Papers, Oct 2003, pp. 155–158.
5. J. Barth, D. Anand, J. Dreibelbis, J. Fifield, K. Gorman, M. Nelms, G. Pomichter, D. Pontius, A 500-MHz multi-banked compliable DRAM macro with direct write and programmable pipleing. JSCC 40(1), 213–222 (Apr 2005).