Resource-Efficient FPGA Implementation of Advanced Encryption Standard
Author:
Affiliation:
1. Ajou University,Department of Electrical and Computer Engineering,Suwon,Republic of Korea
Funder
National Research Foundation of Korea
IC Design Education Center
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937497.pdf?arnumber=9937497
Reference18 articles.
1. A combinational logic implementation of S-box of AES
2. Advanced Encryption Standard (AES) Engine PG383 (v1.1);xlinx;LogiCORE IP Product Guide,2020
3. Low Power AES Using 8-Bit and 32-Bit Datapath Optimization for Small Internet-of-Things (IoT)
4. AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption
5. 692-nW Advanced Encryption Standard (AES) on a 0.13-$\mu$m CMOS
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1. Novel High Throughput-to-Area Efficiency and Strong-Resilience Datapath of AES for Lightweight Implementation in IoT Devices;IEEE Internet of Things Journal;2024-05-15
2. Meltrix: A RRAM-Based Polymorphic Architecture Enhanced by Function Synthesis;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
3. Area-Efficient Intellectual Property (IP) Design of Advanced Encryption Standard;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-10
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