Area-Efficient Intellectual Property (IP) Design of Advanced Encryption Standard-Reference-Cited by-同舟云学术

Area-Efficient Intellectual Property (IP) Design of Advanced Encryption Standard

Published:2023-10 Issue:10 Volume:70 Page:3797-3801
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Lee Useok¹^ORCID,Kim Ho Keun¹^ORCID,Lee Jeahack²^ORCID,Sunwoo Myung Hoon¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Ajou University, Suwon, South Korea

2. SoC Platform Research Center, Korea Electronics Technology Institute, Seongnam, South Korea

Funder

National Research and Development Program through the National Research Foundation of Korea

Ministry of Science and ICT, South Korea

Ministry of Science and Information and Communications Technology (MSIT), South Korea

Information Technology Research Center (ITRC) Support Program supervised by the Institute for Information and Communications Technology Planning and Evaluation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10262390/10178017.pdf?arnumber=10178017

Reference17 articles.

1. Resource-Efficient FPGA Implementation of Advanced Encryption Standard

2. AES S-Box Hardware With Efficiency Improvement Based on Linear Mapping Optimization

3. A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence

4. A combinational logic implementation of S-box of AES

5. Area-Efficient Nano-AES Implementation for Internet-of-Things Devices

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