HW2VEC: a Graph Learning Tool for Automating Hardware Security-Reference-Cited by-同舟云学术

HW2VEC: a Graph Learning Tool for Automating Hardware Security

Published:2021-12-12 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
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Author:

Yu Shih-Yuan¹,Yasaei Rozhin¹,Zhou Qingrong¹,Nguyen Tommy¹,Al Faruque Mohammad Abdullah¹

Affiliation:

1. University of California,Department of Electrical Engineering and Computer Science,Irvine,California,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9702149/9702266/09702281.pdf?arnumber=9702281

Reference55 articles.

1. Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL

2. Formal verification of taint-propagation security properties in a commercial soc design;subramanyan;Proc of the Conference on Design Automation and Test in Europe (DATE),0

3. Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage

4. Detecting malicious modifications of data in third-party intellectual property cores

5. Security analysis of integrated circuit camouflaging

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