Author:
Seta K.,Hara H.,Kuroda T.,Kakumu M.,Sakurai T.
Cited by
24 articles.
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1. Low-Power Deep-Submicron CMOS Adder Using Optimized Delay Universal Gates;Advances in Automation, Signal Processing, Instrumentation, and Control;2021
2. Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-10
3. POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT;Journal of Circuits, Systems and Computers;2014-06-18
4. On-Chip Power Gating Technique;Green Computing with Emerging Memory;2012-09-27
5. Introduction;Green Computing with Emerging Memory;2012-09-27