Low-Power Deep-Submicron CMOS Adder Using Optimized Delay Universal Gates
Author:
Publisher
Springer Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-15-8221-9_47
Reference19 articles.
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4. Keshavarzi A, Narendra S, Borkar S, Hawkins C, Roy K, De V (1999) Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC’s. In: Proceedings of the international symposium on low power electronics and design, pp 252–254
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