HDL Environment for the Synthesis of 2-Dimensional and 3- Dimensional Network on Chip Mesh Router Architecture-Reference-Cited by-同舟云学术

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HDL Environment for the Synthesis of 2-Dimensional and 3- Dimensional Network on Chip Mesh Router Architecture

Published:2024-05-09 Issue: Volume: Page:55-60
ISSN:
Container-title:2024 International Conference on Communication, Computer Sciences and Engineering (IC3SE)
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Author:

Kumari Shweta¹,Rajput Kapil²,Singh Gurwinder³,Jain Arpit⁴,Sachi Savya⁵,Manwal Manika⁶

Affiliation:

1. Shri Fanishwar Nath Renu Engineering College,Department of Computer Science & Engineering,Araria,Bihar,India

2. Graphic Era Hill University,Computer Science and Engineering,Dehradun,Uttarakhand,India

3. Chandigarh University,Department of AITCSE,Mohali,Punjab,India

4. Koneru Lakshmaiah Education Foundation,Department of Computer Science & Engineering,Vaddeswaram,AP,India

5. L N Mishra College of Business Management,Department of Information Technology,Muzaffarpur,Bihar,India

6. Graphic Era Deemed to be University,Computer Science and Engineering,Dehradun,Uttarakhand,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10592860/10592845/10593654.pdf?arnumber=10593654

Reference33 articles.

1. A survey on application mapping strategies for Network-on-Chip design

2. Networks on Chips: Structure and Design Methodologies

3. Network-on-Chip design and synthesis outlook

4. On-chip communication architecture exploration

5. Low cost fault-tolerant routing algorithm for Networks-on-Chip

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