A 21-Gb/s PAM-3 Driver Using ZQ Calibration with Middle-Level Calibration to Improve Level Separation Mismatch Ratio
Author:
Affiliation:
1. Kwangwoon University,Electronics and Communications Engineering,Seoul,Korea
Funder
IITP
National Research Foundation of Korea
IC Design Education Center
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10211092/10212431/10212749.pdf?arnumber=10212749
Reference12 articles.
1. 30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links
2. High-speed serial link challenges using multi-level signaling
3. Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters
4. A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation
5. A 20-Gb/s, 0.66-pJ/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45nm SOI CMOS;proesel;Symp VLSI Circuits Dig Tech Papers,2011
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