High-speed serial link challenges using multi-level signaling-Reference-Cited by-同舟云学术

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High-speed serial link challenges using multi-level signaling

Published:2015-10 Issue: Volume: Page:
ISSN:
Container-title:2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)
language:
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Author:

Dikhaminjia N.,He J.,Hernandez E.,Tsiklauri M.,Drewniak J.,Chada A.,Zvonkin M.,Mutnury B.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7331575/7347113/07347129.pdf?arnumber=7347129

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Comparisons of Equalization Performances and CM Suppression on NRZ and PAM4 Signals using Wideband DME-CMF;2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa);2024-05-20

2. Statistical Eye Diagrams for High-Speed Interconnects of Packages: A Review;IEEE Access;2024

3. A 21-Gb/s PAM-3 Driver Using ZQ Calibration with Middle-Level Calibration to Improve Level Separation Mismatch Ratio;2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC);2023-06-25

4. Analytical method for joint optimization of FFE and DFE equalizations for multi-level signals;Journal of Electrical Engineering;2022-08-01

5. An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation;Electronics;2021-07-24

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