Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction
Author:
Affiliation:
1. Chair of Semiconductor Test and Reliability (STAR), University of Stuttgart, Stuttgart, Germany
2. Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/10164683/10106505.pdf?arnumber=10106505
Reference42 articles.
1. All-in-Memory Brain-Inspired Computing Using FeFET Synapses
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