Affiliation:
1. Department of Electrical Engineering Indian Institute of Technology Kanpur UP 208016 India
2. Semiconductor Test and Reliability (STAR) University of Stuttgart 70550 Stuttgart Germany
3. Chair of AI Processor Design TUM School of Computation Information and Technology Munich Institute of Robotics and Machine Intelligence Technical University of Munich 80333 Munich Germany
Abstract
Monolithic three‐dimensional (M3D) integration advances integrated circuits by enhancing density and energy efficiency. Ferroelectric thin‐film transistors (Fe‐TFTs) attract attention for neuromorphic computing and back‐end‐of‐the‐line (BEOL) compatibility. However, M3D faces challenges like increased runtime temperatures due to limited heat dissipation, impacting system reliability. This work demonstrates the effect of temperature impact on single‐gate (SG) Fe‐TFT reliability. SG Fe‐TFTs have limitations such as read‐disturbance and small memory windows, constraining their use. To mitigate these, dual‐gate (DG) Fe‐TFTs are modeled using technology computer‐aided design, comparing their performance. Compute‐in‐memory (CIM) architectures with SG and DG Fe‐TFTs are investigated for deep neural networks (DNN) accelerators, revealing heat's detrimental effect on reliability and inference accuracy. DG Fe‐TFTs exhibit about 4.6x higher throughput than SG Fe‐TFTs. Additionally, thermal effects within the simulated M3D architecture are analyzed, noting reduced DNN accuracy to 81.11% and 67.85% for SG and DG Fe‐TFTs, respectively. Furthermore, various cooling methods and their impact on CIM system temperature are demonstrated, offering insights for efficient thermal management strategies.
Reference32 articles.
1. Physics for neuromorphic computing
2. S.Kumar S.Chatterjee S.Thomann P. R.Genssler Y. S.Chauhan H.Amrouch in2022 IFIP/IEEE 30th Int. Conf. Very Large Scale Integration (VLSI‐SoC) IEEE Piscataway NJ2022 pp.1–6.
3. Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction
4. S.Dutta H.Ye W.Chakraborty Y.‐C.Luo M.San Jose B.Grisafe A.Khanna I.Lightcap S.Shinde S.Yu S.Datta in2020 IEEE Int. Electron Devices Meeting (IEDM) IEEE Piscataway NJ2020 pp.36.4.1–36.4.4.
5. The era of hyper-scaling in electronics