PL-NPU: An Energy-Efficient Edge-Device DNN Training Processor With Posit-Based Logarithm-Domain Computing
Author:
Affiliation:
1. Beijing Innovation Center for Future Chip and the Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing, China
Funder
NSFC
National Key Research and Development Program of China
Beijing Science and Technology Project
Beijing Advanced Innovation Center
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/9904939/09803862.pdf?arnumber=9803862
Reference47 articles.
1. Evaluating the Hardware Cost of the Posit Number System
2. An extended precision logarithmic number system
3. The Accuracy of Floating Point Summation
4. A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor
5. Evaluations on Deep Neural Networks Training Using Posit Number System
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